Performance Enhancement of Forming-Free ReRAM Devices Using 3D Nanoparticles

ABSTRACT

Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

This application claims priority to U.S. Provisional Patent ApplicationNo. 61/785,069 entitled “ReRAM Materials” filed on Mar. 14, 2013, whichis incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates generally to nonvolatile memory elements, andmore particularly, to methods for forming resistive switching memoryelements used in nonvolatile memory devices

BACKGROUND

Nonvolatile memory elements are used in systems in which persistentstorage is required. For example, digital cameras use nonvolatile memorycards to store images and digital music players use nonvolatile memoryto store audio data. Nonvolatile memory is also used to persistentlystore data in computer environments. Nonvolatile memory is often formedusing electrically-erasable programmable read only memory (EPROM)technology. This type of nonvolatile memory contains floating gatetransistors that can be selectively programmed or erased by applicationof suitable voltages to their terminals.

As fabrication techniques improve, it is becoming possible to fabricatenonvolatile memory elements with increasingly smaller dimensions.However, as device dimensions shrink, scaling issues are posingchallenges for traditional nonvolatile memory technology. This has ledto the investigation of alternative nonvolatile memory technologies,including resistive switching nonvolatile memory.

Resistive memory device, e.g., resistive switching nonvolatile randomaccess memory (ReRAM) is formed using memory elements that have two ormore stable states with different resistances. Bistable memory has twostable states. A bistable memory element can be placed in a highresistance state or a low resistance state by application of suitablevoltages or currents. Voltage pulses are typically used to switch thememory element from one resistance state to the other. Nondestructiveread operations can be performed to ascertain the value of a data bitthat is stored in a memory cell.

Resistive switching based on transition metal oxide switching elementsformed of metal oxide films has been demonstrated. Although metal oxidefilms such as these exhibit bistability, the resistance of these filmsand the ratio of the high-to-low resistance states can be insufficientto be of use within a practical nonvolatile memory device. For instance,the resistance states of the metal oxide film should preferably besignificant as compared to that of the system (e.g., the memory deviceand associated circuitry) so that any change in the resistance statechange is perceptible. The variation of the difference in resistivestates is related to the resistance of the resistive switching layer.Therefore, a low resistance metal oxide film may not form a reliablenonvolatile memory device. For example, in a nonvolatile memory that hasconductive lines formed of a relatively high resistance metal such astungsten, the resistance of the conductive lines may overwhelm theresistance of the metal oxide resistive switching element. Therefore,the state of the bistable metal oxide resistive switching element may bedifficult or impossible to sense.

Therefore, there is a need for a memory device that can meet the designcriteria for advanced memory devices.

SUMMARY

In some embodiments, methods and devices for forming resistive memorydevices are provided. The resistive memory devices can include one ormore array of metal nanoparticles in a switching layer, which isdisposed between two electrodes. The switching layer may be depositedusing various techniques, such as sputtering and atomic layer deposition(ALD).

In some embodiments, a resistive random access memory cell includes afirst layer operable as a first electrode, a second layer operable as asecond electrode, and a third layer operable as a resistive switchinglayer and disposed between the first layer and the second layer. Thethird layer includes arrays of metal nanoparticles. The arrays of metalnanoparticles can be formed using a micelle solution.

The generation of the nanoparticles can be controlled in multipledimensions to achieve desirable performance characteristics, such as lowpower consumption as well as low and consistent switching currents. Forexample, the vertical spacing of the nanoparticles can be achieved bythe thickness of the portion of the switching layer between two adjacentarrays. The lateral spacing of the nanoparticles can be achieved by thepreparation of the micelle solution, such as using surfactant solutionswith different copolymer chain length. The size of the nanoparticles canalso be achieved by the preparation of the micelle solution, such as theconcentration of metal in the micelle solution.

BRIEF DESCRIPTION OF THE DRAWINGS

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. The drawings are not to scale and the relative dimensionsof various elements in the drawings are depicted schematically and notnecessarily to scale.

The techniques of the present invention can readily be understood byconsidering the following detailed description in conjunction with theaccompanying drawings, in which:

FIGS. 1A-1C illustrate a schematic representation of a ReRAM operationaccording to some embodiments.

FIG. 2 illustrates a plot of a current passing through a unipolar ReRAMcell as a function of a voltage applied to the ReRAM cell according tosome embodiments.

FIGS. 3A-3C illustrate a schematic representation of an operation of anembedded nanoparticles memory structure according to some embodiments.

FIG. 4 illustrates a plot of a current passing through a unipolar ReRAMcell having embedded nanoparticles according to some embodiments.

FIGS. 5A-5F illustrate various configurations of memory structureshaving embedded nanoparticles according to some embodiments.

FIGS. 6A-6H illustrate a process flow for forming a memory structurehaving embedded nanoparticles according to some embodiments.

FIG. 7 illustrates a flowchart for forming a memory device according tosome embodiments.

FIG. 8 illustrates a micelle solution according to some embodiments.

FIG. 9 illustrates a schematic representation of atomic layer depositionapparatus for fabricating ReRAM cells according to some embodiments.

FIGS. 10A-10B illustrate a schematic representation of resistiveswitching ReRAM cell according to some embodiments.

FIGS. 11A-11B illustrate flowcharts for fabricating a resistiveswitching layer of a memory device according to some embodiments.

FIG. 12 illustrates a flowchart for forming a memory device according tosome embodiments.

FIG. 13A-13B illustrates memory arrays according to some embodiments.

DETAILED DESCRIPTION

A detailed description of one or more embodiments is provided belowalong with accompanying figures. The detailed description is provided inconnection with such embodiments, but is not limited to any particularexample. The scope is limited only by the claims and numerousalternatives, modifications, and equivalents are encompassed. Numerousspecific details are set forth in the following description in order toprovide a thorough understanding. These details are provided for thepurpose of example and the described techniques may be practicedaccording to the claims without some or all of these specific details.For the purpose of clarity, technical material that is known in thetechnical fields related to the embodiments has not been described indetail to avoid unnecessarily obscuring the description.

In some embodiments, methods to fabricate resistive memory devices, andthe resistive memory devices fabricated from the methods, are provided.The resistive memory devices can include two electrodes covering aswitching layer having embedded metal nanoparticles. The metalnanoparticles can act as seeds for the conductive filaments in theswitching layer, which can cause the change in resistance of theswitching layer due to the formation and rupture of the conductivefilaments. The incorporation of metal nanoparticles in the switchinglayer can be controlled in a 3D deposition process, e.g., the lateralspacing of the nanoparticles along the surface of the devices and thevertical spacing of the nanoparticles in the direction between theelectrodes.

The embedded metal nanoparticles can facilitate the formation of theconductive filaments, for example, due to the formation of theconductive filaments between the metal nanoparticles. Since thedistances between the nanoparticles can be controlled during the devicefabrication process, the initial formation of the conductive filaments,e.g., the application of a forming voltage to create the conductivefilaments, can be reduced or eliminated. Further, the power requirementfor the memory devices can be reduced due to the reduced distances ofthe conductive filaments.

The embedded metal nanoparticles can also confine the locations of theconductive filaments. Thus the resistive memory devices can havecontrolled filament nucleation and growth to provide improved uniformityof resistive switching properties.

A ReRAM cell exhibiting resistive switching characteristics generallyincludes multiple layers formed into a stack. The structure of thisstack is sometimes described as a Metal-Insulator-Metal (MIM) structure.Specifically, the stack includes two conductive layers operating aselectrodes. These layers may include metals and/or other conductivematerials. The stack also includes an insulator layer disposed inbetween the electrode. The insulator layer exhibits resistive switchingproperties characterized by different resistive states of the materialforming this layer. As such, this insulator layer is often referred toas a resistive switching layer. These resistive states may be used torepresent one or more bits of information. The resistance switchingproperties of the insulator layer are believed to depend on variousdefects' presence and distribution inside this layer. For example,different distribution of oxygen vacancies in the layer may reflectdifferent resistance states of the layer, and these states may besufficiently stable for memory application.

To achieve a certain concentration of defects in the resistanceswitching layer, the layer has been conventionally deposited withdefects already present in the layer, i.e., with preformed defects. Inother words, defects are introduced into the layer during its formation.For example, tightly controlled Atomic Layer Deposition (ALD), PhysicalVapor Deposition (PVD), or some other low-temperature process to remainwithin a Back End of Line (BEOL) thermal budget may be used to depositthe insulator layer of the stack. It may be difficult to precisely andrepeatedly control formation of these defects particularly in very thinresistance switching layers (e.g., less than 100 Angstroms). Forexample, when ALD is used to form resistance switching layers, someunreacted precursors may leave carbon-containing residues that impactresistance characteristics of the deposition layers and ReRAM cellsincluding these layers. Furthermore, achieving precise partialsaturation repeatedly may be very difficult if possible at all. In thecase of PVD, sputtering targets tend to wear out influencing thedeposition rates and creating variation in resulting resistanceswitching layers.

A brief description of ReRAM cells and their switching mechanisms areprovided for better understanding of various features and structuresassociated with methods of forming nonvolatile memory elements furtherdescribed below. ReRAM is a non-volatile memory type that includesdielectric material exhibiting resistive switching characteristics. Adielectric, which is normally insulator, can be made to conduct throughone or more filaments or conduction paths formed after application of asufficiently high voltage. The conduction path formation can arise fromdifferent mechanisms, including defects, metal migration, and othermechanisms further described below. Once the one or more filaments orconduction paths are formed in the dielectric component of a memorydevice, these filaments or conduction paths may be reset (or brokenresulting in a high resistance) or set (or re-formed resulting in alower resistance) by applying certain voltages. Without being restrictedto any particular theory, it is believed that resistive switchingcorresponds to migration of defects within the resistive switching layerand, in some embodiments, across one interface formed by the resistiveswitching voltage, when a switching voltage is applied to the layer.

FIGS. 1A-1C illustrate a schematic representation of a ReRAM operationaccording to some embodiments. A basic building unit of a memory deviceis a stack having a capacitor like structure. A ReRAM cell includes twoelectrodes and a dielectric positioned in between these two electrodes.FIG. 1A illustrates a schematic representation of ReRAM cell 100including top electrode 102, bottom electrode 106, and resistanceswitching layer 104 provided in between top electrode 102 and bottomelectrode 106. It should be noted that the “top” and “bottom” referencesfor electrodes 102 and 106 are used solely for differentiation and notto imply any particular spatial orientation of these electrodes. Oftenother references, such as “first formed” and “second formed” electrodesor simply “first” and “second”, are used identify the two electrodes.ReRAM cell 100 may also include other components, such as an embeddedresistor, diode, and other components. ReRAM cell 100 is sometimesreferred to as a memory element or a memory unit.

Top electrode 102 and bottom electrode 106 may be used as conductivelines within a memory array or other types of devices that ReRAM cell isintegrated into. As such, electrode 102 and 106 are generally formedfrom conductive materials. As stated above, one of the electrodes may bereactive electrode and act as a source and as a reservoir of defects forthe resistive switching layer. That is, defects may travel through aninterface formed by this electrode with the resistive switching layer(i.e., the reactive interface). The other interface of the resistiveswitching layer may be inert and may be formed with an inert electrodeor a diffusion barrier layer.

Resistance switching layer 104 which may be initially formed from adielectric material and later can be made to conduct through one or moreconductive paths formed within the layer by applying first a formingvoltage and then a switching voltage. To provide this resistiveswitching functionality, resistance switching layer 104 includes aconcentration of electrically active defects 108, which may be at leastpartially provided into the layer during its fabrication. For example,some atoms may be absent from their native structures (i.e., creatingvacancies) and/or additional atoms may be inserted into the nativestructures (i.e., creating interstitial defects). Charge carriers may bealso introduced as dopants, stressing lattices, and other techniques.Regardless of the types all charge carriers are referred to as defects108.

In some embodiments, these defects may be utilized for ReRAM cellsoperating according to a valence change mechanism, which may occur inspecific transition metal oxides, nitrides, and oxy-nitrides. Forexample, defects may be oxygen vacancies triggered by migration ofoxygen anions. Migrations of oxygen anions correspond to the motion ofcorresponding oxygen vacancies that are used to create and breakconductive paths. A subsequent change of the stoichiometry in thetransition metal oxides leads to a redox reaction expressed by a valencechange of the cation sublattice and a change in the electricalconductivity. In this example, the polarity of the pulse used to performthis change determines the direction of the change, i.e., reduction oroxidation. Other resistive switching mechanisms include bipolarelectrochemical metallization mechanisms and thermochemical mechanisms,which leads to a change of the stoichiometry due to a current-inducedincrease of the temperature. Some of these mechanisms will be furtherdescribed below with reference to FIGS. 1A-1C. In the describedexamples, top electrode 102 is reactive, while bottom electrode 106 isinert or is separated from resistive switching layer 104 by a diffusionbarrier layer (not shown). One having ordinary skills in the art wouldunderstand that other arrangements are possible as well and within thescope of this disclosure.

Specifically, FIG. 1A is a schematic representation of ReRAM cell 100prior to initial formation of conductive paths, in accordance with someembodiments. Resistive switching layer 104 may include some defects 108.Additional defects 108 may be provided within top electrode 102 and maybe later transferred to resistive switching layer 104 during theformation operation. In some embodiments, the resistive switching layer104 has substantially no defects prior to the forming operation and alldefects are provided from top electrode 102 during forming. Bottomelectrode 106 may or may not have any defects. It should be noted thatregardless of the presence or absence of defects in bottom electrode106, substantially no defects are exchanged between bottom electrode 106and resistive switching layer 104 during forming and/or switchingoperations.

During the forming operation, ReRAM cell 100 changes its structure fromthe one shown in FIG. 1A to the one shown in FIG. 1B. This changecorresponds to defects 108 being arranged into one or more continuouspaths within resistive switching layer 104 as, for example,schematically illustrated in FIG. 1B. Without being restricted to anyparticular theory, it is believed that defects 108 can be reorientedwithin resistance switching layer 104 to form these conductive paths 110as, for example, schematically shown in FIG. 1B. Furthermore, some orall defects 108 forming the conductive paths may enter resistiveswitching layer 104 from top electrode 102. For simplicity, all thesephenomena are collectively referred to as reorientation of defectswithin ReRAM cell 100. This reorientation of defects 108 occurs when acertain forming voltage 104 is applied to electrodes 102 and 106. Insome embodiments, the forming operation also conducted at elevatedtemperatures to enhanced mobility of the defects within ReRAM cell 100.In general, the forming operation is considered to be a part of thefabrication of ReRAM cell 100, while subsequent resistive switching isconsidered to be a part of operation of ReRAM cell.

Resistive switching involves breaking and reforming conductive pathsthrough resistive switching layer 104, i.e., switching between the stateschematically illustrated in FIG. 1B and the state schematicallyillustrated in FIG. 1C. The resistive switching is performed by applyingswitching voltages to electrodes 102 and 106. Depending on magnitude andpolarity of these voltages, conductive path 110 may be broken orre-formed. These voltages may be substantially lower than formingvoltages (i.e., voltages used in the forming operation) since much lessmobility of defects is needed during switching operations. For example,hafnium oxide based resistive layers may need about 7 Volts during theirforming but can be switched using voltages less than 4 Volts.

The state of resistive switching layer 104 illustrated in FIG. 1B isreferred to as a low resistance state (LRS), while the state illustratedin FIG. 1C is referred to as a high resistance state (HRS). Theresistance difference between the LRS and HRS is due to different numberand/or conductivity of conductive paths that exists in these states,i.e., resistive switching layer 104 has more conductive paths and/orless resistive conductive paths when it is in the LRS than when it is inthe HRS. It should be noted that resistive switching layer 104 may stillhave some conductive paths while it is in the HRS, but these conductivepaths are fewer and/or more resistive than the ones corresponding to theLRS.

When switching from its LRS to HRS, which is often referred to as areset operation, resistive switching layer 104 may release some defectsinto top electrode 102. Furthermore, there may be some mobility ofdefects within resistive switching layer 104. This may lead to thinningand, in some embodiments, breakages of conductive paths as shown in FIG.1C. Depending on mobility within resistive switching layer 104 anddiffusion through the interface formed by resistive switching layer 104and top electrode 102, the conductive paths may break closer to theinterface with bottom electrode 106, somewhere within resistiveswitching layer 104, or at the interface with top electrode 102. Thisbreakage generally does not correspond to complete dispersion of defectsforming these conductive paths and may be a self limiting process, i.e.,the process may stop after some initial breakage occurs.

When switching from its HRS to LRS, which is often referred to as a setoperation, resistive switching layer 104 may receive some defects fromtop electrode 102. Similar to the reset operation described above, theremay be some mobility of defects within resistive switching layer 104.This may lead to thickening and, in some embodiments, reforming ofconductive paths as shown in FIG. 1B. In some embodiments, a voltageapplied to electrodes 102 and 104 during the set operation has the samepolarity as a voltage applied during the reset operation. This type ofswitching is referred to as unipolar switching. Some examples of cellsthat exhibit unipolar switching behavior include resistive switchinglayers formed from most metal oxide and having inert electrodes at bothsides, e.g., Pt/MeO_(x)/Pt. Alternatively, a voltage applied toelectrodes 102 and 104 during the set operation may have differentpolarity as a voltage applied during the reset operation. This type ofswitching is referred to as bipolar switching. Some examples of cellsthat exhibit bipolar switching behavior include resistive switchinglayers formed from MeOx having one inert electrode and one reactiveelectrode, e.g., TiN/MeOx/Pt and TiN/MeOx/poly-Si.

FIG. 2 illustrates a plot of a current passing through a unipolar ReRAMcell as a function of a voltage applied to the ReRAM cell according tosome embodiments. A metal-insulator-metal (MIM) structure 210 can befirst fabricated with an amount of defects embedded in the insulatorlayer. A voltage or current 220 can be applied to the MIM structure toform a resistive memory device from the MIM structure, for example, bymaking the insulator layer becoming a switching layer. By applying aforming voltage V_(form), the randomly distributed defects can betransitioned 250 to lower resistance configurations, for example, in theform of filaments 230.

The lower resistance configurations can be characterized as a lowresistance state (LRS) 234 for the resistive memory device, whichpersists even when the voltage is reduced. The LRS can represent a logicstate of the memory device, such as a logic zero (“0”).

At LRS, when another voltage, e.g., V_(reset) is applied, the resistancecan be transitioned 235 to a high resistance state (HRS), which persistseven when the voltage is reduced. The HRS can represent another logicstate of the memory device, such as a logic one (“1”). The reset voltageV_(reset) is smaller then the forming voltage V_(form).

At HRS, when another voltage, e.g., V_(set) is applied, the resistancecan be transitioned 215 back to the low resistance state (LRS), whichpersists even when the voltage is reduced. The set voltage V_(set) isalso smaller then the forming voltage V_(form).

Overall, the ReRAM cell may be switched back and forth between its LRSand HRS many times. For example, when it is desired to turn “ON” thecell, e.g., to have a LRS, a set operation can be performed through theapplication of a set voltage V_(set) to the electrodes. Applying the setvoltage forms one or more conductive paths in the resistance switchinglayer as shown in 230. If it is desired to turn “OFF” the ReRAM cell,e.g., to change to HRS, a reset operation can be preformed through theapplication of a reset voltage V_(reset) to the electrodes. Applying thereset voltage can destroy the conductive paths in the resistanceswitching layer as shown in 250.

The polarity of the reset voltage and the set voltage may be the same inunipolar memory devices, or may be different in bipolar devices (notshown). Without being restricted to any particular theory, it isbelieved that the resistive switching occurs due to filament formationand destruction caused by the application of electrical field.

Read operations may be performed in each of these states (between theswitching operations) one or more times or not performed at all. Duringthe read operation, the state of the ReRAM cell or, more specifically,the resistive state of its resistance of resistance switching layer canbe sensed by applying a sensing voltage to its electrodes. The sensingvoltage is sometimes referred to as a read voltage V_(read).

In some embodiments, the set voltage V_(set) is between about 100 mV and10V or, more specifically, between about 500 mV and 5V. The length ofset voltage pulses may be less than about 100 milliseconds or, morespecifically, less than about 5 milliseconds and even less than about100 nanoseconds. The read voltage V_(read) may be between about 0.1 and0.5 of the set voltage V_(set). In some embodiments, the read currents(I_(ON) and I_(OFF)) are greater than about 1 mA or, more specifically,is greater than about 5 mA to allow for a fast detection of the state byreasonably small sense amplifiers. The length of read voltage pulse maybe comparable to the length of the corresponding set voltage pulse ormay be shorter than the write voltage pulse. ReRAM cells should be ableto cycle between LRS and HRS between at least about 10³ times or, morespecifically, at least about 10⁷ times without failure. A data retentiontime should be at least about 5 years or, more specifically, at leastabout 10 years at a thermal stress up to 85° C. and small electricalstress, such as a constant application of the read voltage. Otherconsiderations may include low current leakage, such as less than about40 A/cm² measured at 0.5 V per 20 Å of oxide thickness in HRS.

Practical applications of ReRAM cells require certain switching, dataretention, and other characteristics. For example, ReRAM cells need tohave low leakage, low switching currents, stable performance over alarge number of switching cycles. It has been found that a composition,morphology, and deposition process of resistive switching layers,together with appropriate electrode materials, have to be specificallytuned to meet these requirements.

In some embodiments, ReRAM cells and methods to fabricate ReRAM cellsare provided with metal oxide switching layers having embeddednanoparticles disposed between electrodes. The embedded nanoparticlesmetal oxide layers can be deposited by atomic layer deposition, withpre-prepared nanoparticles coating during the deposition. The embeddednanoparticles can be specifically designed to provide a metal oxidelayer with desirable performance characteristics. In some embodiments,the forming process can be eliminated, e.g., the as-deposited memorycells can be readily programmed without the application of a formingvoltage. In some embodiments, an operating voltage, e.g., a switchingvoltage, can be less than about 2 V, while the corresponding switchingcurrent can be less than about 100 μA, which can provide improved(lower) power characteristics.

The switching layers can include a metal oxide layer, such as hafniumoxide, aluminum oxide, or a combination of hafnium oxide and aluminumoxide. Other metal oxides can be used, such as titanium oxide andzirconium oxide. Other impurities can be provided to the switchinglayers, such as nitrogen. The addition of nitrogen may be used forcontrolling the amount of oxygen vacancies in the switching layer andfor maintaining this layer in an amorphous state.

The switching layer may be deposited using various techniques, such assputtering and atomic layer deposition (ALD). The ALD approaches may befurther divided into nanolamination ALD or staggered pulse ALD. Thefollowing description of these approaches is directed to formation ofhafnium-aluminum metal oxides. However, one having ordinary skills inthe art would understand that such processes may be varied to form othermetal oxides, such as hafnium oxide, aluminum oxide, titanium oxide,zirconium oxide, or any combinations thereof.

Nanolamination may involve deposition of one or more hafnium oxidelayers and, separately, one or more aluminum oxide layers to form astack. The stack is then annealed in order to intermix these layers. Insome embodiments, the resulting layer (i.e., after the annealing) issubstantially homogeneous. For example, a hafnium containing precursor,such as Tetrakis Dimethylamino Hafnium (TDMAHf), TetrakisEthylmethylamino Hafnium (TEMAHf), and/or hafnium tetrachloride may beintroduced into an ALD chamber followed by an oxidizer, such as water orozone. A hafnium oxide layer may be formed at this point. This hafniumprecursor—oxidizer cycle may be repeated multiple times depending on adesired concentration of hafnium in a resulting base layer (andsubsequently in the resistive switching layer). An aluminum containingprecursor, such as a Trimethyl aluminum (TMA), is then introduced into achamber, followed by introduction of an oxidizer, such as water orozone. As such, a separate layer of aluminum oxide is formed over one ormore layers of hafnium oxide. Of course, this deposition order may bereversed, and one or more aluminum oxide layers may be deposited priorto deposition of one or more hafnium oxide layers. Furthermore,deposition of one or more aluminum oxides layers and one or more hafniumoxide layers may be repeated a number of times until the switching layerbecomes sufficiently thick. The composition of the switching layer canbe modified by controlling how many aluminum oxides layers and how manyhafnium oxides layers are deposited and form the switching layer. Forexample, a switching layer may be formed by alternating depositions offive hafnium oxide layers per one aluminum oxide layer. Furthermore,distribution of hafnium, aluminum, oxygen, and nitrogen in the resultingresistive switching layer may be controlled by specific order of ALDcycles.

A staggered pulse deposition may involve introducing a hafniumcontaining precursor into an ALD chamber followed by introducing analuminum containing precursor into the ALD chamber. It should be notedthat both metal precursors are introduced into the chamber prior to anyoxidation of any one of the two precursors. In some embodiments, analuminum containing precursor is introduced into the chamber prior tointroducing a hafnium containing precursor. This order depends on thetype of metal precursors (their adsorption characteristics, size,reactivity, and other like characteristics) and desired composition ofthe resulting switching layer. For example, if TMA is introduced intothe chamber prior to TDMAHf, then the resulting switching layer containspredominantly aluminum oxide with very little hafnium present. However,if TDMAHf is introduced into the chamber prior to TMA, then theresulting switching layer can contain more hafnium than aluminum, e.g.,higher atomic percent of hafnium oxide relative to the total amount ofmetals present in the layer.

Once both metal precursors are allowed to adsorb on the surface, anoxidizer is introduced into the chamber to convert both precursors intocorresponding oxides. As such, a film containing both aluminum andhafnium oxides may be formed. This cycle including introduction of twometal precursors followed by introduction of an oxidizer may be repeateda number of times to build a switching layer having a desired thickness.The switching layer composition generally depends on the nature ofprecursors used in this approach. The resulting switching layer can beannealed, for example, at temperatures between 400 and 750 C.

FIGS. 3A-3C illustrate a schematic representation of an operation of anembedded nanoparticles memory structure according to some embodiments.In FIG. 3A, a ReRAM cell 300 including top electrode 330, bottomelectrode 310, and resistance switching layer 320 provided in betweentop electrode 330 and bottom electrode 310. ReRAM cell 300 may alsoinclude other components, such as an embedded resistor, diode, and othercomponents. ReRAM cell 300 is sometimes referred to as a memory elementor a memory unit.

As discussed above with respect to FIGS. 1A-1C, electrode 330 and 310can be formed from conductive materials. Resistance switching layer 320can be formed from a dielectric material, which includes a concentrationof electrically active defects 321, which may be at least partiallyprovided into the layer during its fabrication. These defects can beused to form conductive filaments.

The resistance switching layer 320 can further include metalnanoparticles 322 and/or 323. For example, the nanoparticles 322 caninclude multiple particles distributed along the direction between thetwo electrodes 310 and 330. The nanoparticles 323 can be distributedwith difference spacing. Other arrangements are possible as well andwithin the scope of this disclosure, such as one layer of nanoparticlesdistributed in the switching layer, or multiple layers of nanoparticles.The spacing of the nanoparticles can be configured to improve aperformance of the memory cell, such as lower power consumption. Themetal nanoparticles can include metal materials such as Au, Cu, Ag, orany other metals. The size of the nanoparticles can be less than 100 nm,such as between 2 and 10 nm, or between 2 and 5 nm.

During a forming operation, ReRAM cell 300 can change its structure toinclude conductive filaments 353 and 352, as shown in FIG. 3B. Since thelengths of the conductive filaments 352 and 353 are shorter than thelengths of the conductive filaments that occur in a switching layerwithout embedded nanoparticles (such as the filaments shown in FIG. 1B),the forming voltage can be reduced or eliminated, e.g., the formingvoltage can be reduced to the programming voltage (e.g., a set voltageV_(set)). For example, short filaments 353 can require a lower formingvoltage, which is less than the forming voltage for a switching layerwithout embedded nanoparticles, but can be still higher than theprogramming voltage. Shorter filaments 352 can require an even lowerforming voltage, which can be similar to the programming voltage, andthus the forming process can be eliminated. The memory cells can beformed during the programming phase, for example, when the memory cellis first used.

The conductive filaments can be broken, for example, by applying aprogramming voltage such as a reset voltage V_(reset). FIG. 3C shows thebroken state 352 and 353 of the filaments. Repeated switching can beperformed by applying set and reset voltages, creating and breakingconductive filaments connecting the two electrodes.

FIG. 4 illustrates a plot of a current passing through a unipolar ReRAMcell having embedded nanoparticles according to some embodiments. Ametal-insulator-metal (MIM) structure 410 can be fabricated with anamount of metal nanoparticles 450 embedded in the insulator layer.

During operation, programming voltages or currents can be applied to theMIM structure 410 to change its resistance. For example, a programmingvoltage, e.g., V_(set), can be applied to make a transition 415 from theinitial configuration 410 to the low resistance state (LRS) 434. The MIMstructure 430 of the low resistance state 434 can include conductivefilaments in the insulator layer, with the nanoparticles acting as seedelements.

When another programming voltage, e.g., V_(reset), is applied, theresistance can be transitioned 435 to a high resistance state (HRS) 412.The MIM structure 450 of the high resistance state 412 can includebroken conductive filaments. The ReRAM cell may be programmed, e.g.,switched back and forth between its LRS and HRS many times through theapplications of set and reset voltages. Applying the set voltage formsone or more conductive paths in the resistance switching layer as shownin 430. Applying the reset voltage can destroy the conductive paths inthe resistance switching layer as shown in 450.

In the figure, the polarity of the reset voltage and the set voltage arethe same, which represents unipolar memory devices. Also, the setvoltage is shown as being higher than the reset voltage. Otherconfigurations can also be used, for example, the reset voltage can behigher than the set voltage, or the polarity of the reset voltage andthe set voltage can be different, as in the case of bipolar devices.Further, the above description is served as an illustration of thepossible operating mechanism, and is intended as a hypothesis for amodel of the present embedded nanoparticle memory structures, and shouldnot affect the validity of the present invention.

In some embodiments, the incorporation of metal nanoparticles can allowforming-free memory devices, e.g., the fabrication of memory devicesthat does not need the forming operation of applying a forming voltage.For example, by providing nanoparticles with a very close spacing, theformation of the conductive filaments can be performed during the deviceprogramming, e.g., by applying the set voltage. Alternatively, thenanoparticles can allow a reduction in forming voltage. For example, byproviding nanoparticles in the switching layer with any spacing ordistribution, the formation of the conductive filaments can befacilitated during the device forming process, e.g., allowing a lowerforming voltage.

FIGS. 5A-5F illustrate various configurations of memory structureshaving embedded nanoparticles according to some embodiments. In FIG. 5A,a memory structure is shown, including a switching layer 520 disposedbetween two electrodes 510 and 530. Nanoparticles 522 are distributedwithin the switching layer 520. The nanoparticles can form multiplelevels between the two electrodes, for example, to reduce the spacing,e.g., the lengths, of the conductive filaments. In the figure, twolevels of nanoparticles are shown, but one or more levels can also beused. Further, one column of nanoparticles is shown, but more columnscan also be used, e.g., arrays of nanoparticles distributed in rows andcolumns in the switching layer 520.

In FIG. 5B, nanoparticles 523 can be distributed in a staggeredconfiguration, which can vary the spacing between the nanoparticles, andas a result, varying the lengths of the conductive filaments whenformed. In FIG. 5C, nanoparticles 524 can be distributed in the middleof the switching layer. Nanoparticles 525 can be placed near theinterfaces of the switching layer with the electrodes. The nanoparticles525 can be disposed in the switching layer and touching the electrodes.For example, after the bottom electrode 510 is deposited, thenanoparticles can be provided on the electrode surface, before or duringthe deposition of the switching layer 520. Alternatively, thenanoparticles 525 can be disposed in the switching layer and separatedfrom the electrodes. For example, after the bottom electrode 510 isdeposited, a thin layer of switching layer can be deposited beforeproviding the nanoparticles. Afterward, additional portions of theswitching layer can be deposited, covering the nanoparticles

In FIG. 5D, nanoparticles 541 can be disposed in the electrodes, forexample, top electrode 530, in addition to other nanoparticles 526 inthe switching layer 520. For example, at the beginning of the depositionof the electrode 530, nanoparticles 541 can be provided so that thenanoparticles 541 can be at least partially embedded in the electrode530. In FIG. 5E, in addition to nanoparticles 542 embedded in electrode530, the nanoparticles 527 can be distributed in rows and columns or canbe distributed in a staggered configuration. In FIG. 5F, nanoparticles543 can be disposed at least partially embedded in top electrode 530,and nanoparticles 544 can be disposed at least partially embedded inbottom electrode 510. The nanoparticles 528 can be distributed in rowsand columns or can be distributed in a staggered configuration. Theconfigurations shown are only for illustrations and examples, and otherconfigurations can also be used. For example, multiple nanoparticles canbe arranged in one or more rows in directions parallel to the surface ofthe electrodes. Multiple nanoparticles can also be arranged in one ormore columns in directions perpendicular to the surface of theelectrodes.

FIGS. 6A-6H illustrate a process flow for forming a memory structurehaving embedded nanoparticles according to some embodiments. In FIG. 6A,a bottom electrode 610 is provided. For example, the electrode 610 canbe deposited on a substrate, or the electrode 610 can be part of thesubstrate, e.g., a component of an underlying structure on thesubstrate. In FIG. 6B, nanoparticles 642 can be deposited on theelectrode 610. Nanoparticles 642 can be deposited by themselves, or canbe embedded in a deposited layer 640. For example, nanoparticles 642 canbe provided in a solution, which then can be coated on the surface ofthe electrode 610. The solution then can be dried, e.g., evaporated,leaving the nanoparticles on the surface (FIG. 6C). In FIG. 6D, aninsulator layer 622 can be deposited over the nanoparticles, thus canembedded the nanoparticles in the insulator layer. The process can berepeated, for example, by depositing another layer of nanoparticles 643(FIG. 6E), another layer of insulator material 623 (FIG. 6F), andanother layer of nanoparticles 644 (FIG. 6G). Electrode 630 can bedeposited over the stack of insulator layer/nanoparticles (FIG. 6H).

FIG. 7 illustrates a flowchart for forming a memory device according tosome embodiments. The described flowchart is a general description oftechniques used to form the memory devices described above. Theflowchart describes techniques for forming a memory device generallyincluding two electrodes and one or more layers disposed there between.Although certain processing techniques and specifications are described,it is understood that various other techniques and modifications of thetechniques described herein may also be used.

In operation 710, a substrate is provided. The substrate can be used forreceiving various deposited components of the ReRAM cell. Furthermore,the same substrate often is used for receiving components of multipleReRAM cells. For example, large memory cell arrays may be formed on thesame substrate. Components of multiple ReRAM cells may be formed fromthe same set of initial layers formed on that substrate. The substratemay include one or more signal lines or contacts. These lines orcontacts provide an electrical connection to a bottom electrode. In someembodiments, the bottom electrode formed in a subsequent operation canserve as a signal line. In a similar manner, a top electrode formed inanother subsequent operation can function as a signal line or it may beconnected to a separate signal line.

The substrate can have a first layer. Alternatively, a first layer canbe deposited on the substrate. The first layer can be operable as afirst or bottom electrode. The bottom electrode can include titaniumnitride or platinum. The bottom electrode may be formed using ALD, CVD,sputtering, or some other techniques. For example, a titanium nitrideelectrode may be formed using sputtering. Deposition of the titaniumnitride electrode may be performed using a titanium target in a nitrogenatmosphere maintained at a pressure of between about 3-20 mTorr. Thepower may be maintained at 350-500 Watts that may result in a depositionrate of about 0.5-5 Angstroms per second (depending on the size of thetarget sample and other process parameters). Some of the providedprocess parameters are for illustrative purposes only and generallydepend on deposited materials, tools, deposition rates, and otherfactors. The bottom electrode may have any thickness, for examplebetween about 5 nm and about 500 nm thick.

In operation 720, a second layer is deposited over the first layer. Thesecond layer can contain a plurality of metal nanoparticles. The metalnanoparticles can include a metal component, such as gold, copper, orsilver. The size of the metal nanoparticles can be less than 100 nm,such as less than 50 or 10 nm, or can be between 1 and 5 nm. The secondlayer can from nanoparticles at the interface of the switching layerwith the electrode. The second layer deposition can be omitted, forexample, in memory configurations that do not require nanoparticles atthe electrode/switching layer interface.

The second layer can be formed by solvent coating. For example, asolution can be prepared, which contains the nanoparticles. The solutioncan be spread over the first layer, for example, by liquid coating,spray coating, or vapor coating. The solvent can be vaporized, forexample, by substrate heating, leaving the nanoparticles dispersed onthe first layer.

In some embodiments, the solution can be prepared by micelle technology.For example, to make gold nanoparticles in micelles, a source of gold,such as gold chloride (AuCl), can be dissolved in a solvent solution.For example, the solvent solution can include an organic solvent such asoctane or butanol. A surfactant, such as a soap, can be added to thesolution to help control the growth of the gold nanoparticles. Thesurfactant can include molecules with a hydrophobic tail and hydrophilichead. Because of this structure, the molecules can form micelles, whichare tiny spheres, arranged on a surface of a sphere. Water can betrapped inside these micelles, which can separate the water inside themicelles from the organic solvent outside the micelles. Since goldchloride is soluble in water, gold chloride can be inside the micelleswith the water.

A reactant can be added to reduce gold chloride to gold. For example,sodium borohydride (NaBH₄) can be added to the solution. Since sodiumborohydride is also water soluble, it can enter the micelles and reactwith gold chloride to form metallic gold. The reaction stops when goldchloride is all reduced. The metallic gold can be crystallized into goldnanoparticles.

The size of the gold nanoparticles can be controlled by theconcentration of gold chloride. A high concentration of gold chloride inthe solution can generate larger gold nanoparticles. Further, the sizeof the gold nanoparticles can be governed by the choice of surfactant.For example, the reaction to reduce gold chloride to gold can be stoppedwhen reaching the size of the micelles. In some embodiments, the sizesof the metal nanoparticles can be controlled, for example, bycontrolling the concentration of the metal source. The size of the metalnanoparticles can affect the performance of the memory cells which havethe nanoparticles embedded in the switching layers.

The density of gold nanoparticles in the solution can be controlled bythe choice of surfactants since the separation between micelles can becontrolled by the block copolymer chain length. For example, asurfactant having a long block copolymer chain length can generate amicelle cluster with large separations between the micelles. In someembodiments, the separation of the metal nanoparticles can becontrolled, for example, by controlling the block copolymer chain lengthof the micelles, e.g., the surfactant solution. The separation of themetal nanoparticles can affect the performance of the memory cells whichhave the nanoparticles embedded in the switching layers. The abovedescription is an illustration of the formation of metal nanoparticlesin the memory structures. Other metal sources, solvents, surfactants,and processes can be used to generate metal nanoparticles suitable formemory cell fabrication.

In operation 730, a third layer can be deposited over the second layer.In some embodiments, the second layer can include only the metalnanoparticles, and thus the third layer can be deposited over the firstlayer in areas not covered by the nanoparticles. The third layer can beoperable as a resistive switching layer, or a portion of the resistiveswitching layer, e.g., additional layers can be deposited to combinewith the third layer to form the resistive switching layer. The thirdlayer can include a metal oxide, such as hafnium oxide, aluminum oxide,zirconium oxide, or any combination thereof.

The third layer may be formed using reactive sputtering, ALD, or othertechniques. For example, a third layer having hafnium oxide may beformed using reactive sputtering by employing a hafnium target in anoxygen atmosphere. Power of 300-1000 Watts (W) may be used to achievedeposition rates of between about 0.1 and 3.0 Angstroms per second.These process parameters are provided as examples and generally dependon deposited materials, tools, deposition rates, and other factors.

In some embodiments, the third layer is formed using ALD. This techniqueincludes one or more cycles, each involving the following two foursteps: introducing one or more first precursors, such as a hafniumcontaining precursor, into the depositing chamber to form an absorbedlayer, followed by purging these precursors reactive agents, and thenintroducing one or more second precursors, such as a oxidation reactant,that will react with the absorbed layer to form a portion of or theentire third layer, followed by purging the second precursor reactiveagents. Selection of precursors and processing conditions depend ondesired composition, morphology, and structure of each portion of theelectrode.

A layer formed during each atomic layer deposition cycle described abovemay be between less than about 0.5 nm thick, such as between 0.02 and0.2 nm. The cycle may be repeated multiple times until the overallsecond layer (and subsequently the thickness of the resistive switchinglayer) reaches it desired thickness. In some embodiments, the thicknessof the third layer can be less than 30 nm, such as less than 10 or 5 nm,e.g., between 0.2 and 3 nm.

ALD techniques are now briefly described to provide better understandingof various processing features. First precursors can be introduced intothe ALD chamber and allowed to flow over the deposition surface (whichmay have previously deposited ALD layers) provided therein. The firstprecursors can include one or more precursors. For example, the firstprecursors can include a hafnium containing precursor. The firstprecursors can include two or more precursors, such as a hafniumcontaining precursor and a reactive precursor such as reactive hydrogenor remote plasma hydrogen.

The first precursors can be introduced in the form of pulses. Betweenthe pulses, the reaction chamber is purged, for example, with an inertgas to remove unreacted precursors, reaction products, and otherundesirable components from the chamber.

The introduced precursor adsorbs (e.g., chemisorbs) on the depositionsurface. Subsequent pulsing with a purging gas removes excess precursorfrom the deposition chamber. In some embodiments, purging is performedbefore full saturation of the substrate surface occurs with theprecursors. In other words, additional precursor molecules could havebeen further adsorbed on the substrate surface if the purging was notinitiated so early. Without being restricted to any particular theory,it is believed that partial saturation can be used to introduce defectsinto the formed layer, e.g., during forming of a resistive switchinglayer.

After the initial precursor pulsing and purging of the first precursors,a subsequent pulse introduces second precursors. The second precursorscan act as reactant agent to react with the adsorbed metal containingmolecules. The second precursors can include one or more precursors. Forexample, the second precursors can include an oxidation agent.

Reaction byproducts and excess reactants are then purged from thedeposition chamber. The saturation during the reaction and purgingstages makes the growth self-limiting. This feature helps to improvedeposition uniformity and conformality and allows more precise controlof the resulting resistive switching characteristics.

The temperature of the substrate during atomic layer deposition may bebetween about 200° C. to 350° C. The precursor may be either in gaseousphase, liquid phase, or solid phase. If a liquid or solid precursor isused, then it may be transported into the chamber an inert carrier gas,such as helium or nitrogen.

Some examples of hafnium containing precursors includebis(tert-butylcyclopentadienyl) dimethyl hafnium (C₂₀H₃₂Hf),bis(methyl-η5-cyclopentadienyl) methoxymethyl hafnium(HfCH₃(OCH₃)[C₅H₄(CH₃)]₂), bis(trimethylsilyl) amido hafnium chloride([[(CH₃)₃Si]₂N]₂HfCl₂), dimethylbis(cyclopentadienyl) hafnium((C₅H₅)₂Hf(CH₃)₂), hafnium isopropoxide isopropanol adduct (C₁₂H₂₈HfO₄),tetrakis(diethylamido) hafnium ([(CH₂CH₃)₂N]₄Hf)—also known as TEMAH,tetrakis(ethylmethylamido) hafnium ([(CH₃)(C₂H₅)N]₄Hf),tetrakis(dimethylamido) hafnium ([(CH₃)₂N]₄Hf)—also known as TDMAH, andhafnium tert-butoxide (HTB). Some hafnium containing precursors can berepresented with a formula (RR′N) 4Hf, where R and R′ are independenthydrogen or alkyl groups and may be the same or different. Some examplesof aluminum containing precursors include aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) (Al(OCC(CH₃)₃CHCOC(CH₃)₃)₃),triisobutyl aluminum ([(CH₃)₂CHCH₂]₃Al), trimethyl aluminum((CH₃)₃Al)—also known as TMA, Tris (dimethyl amido) aluminum(Al(N(CH₃)₂)₃). The nitrogen containing oxidizing agent may includeammonia (NH₃), which in some embodiments may be mixed with carbonmonoxide (CO). Some examples of suitable oxidizing agents containingoxygen include water (H2O), peroxides (organic and inorganic, includinghydrogen peroxide H₂O₂), oxygen (O₂), ozone (O₃), oxides of nitrogen(NO, N₂O, NO₂, N₂O₅), alcohols (e.g., ROH, where R is a methyl, ethyl,propyl, isopropyl, butyl, secondary butyl, or tertiary butyl group, orother suitable alkyl group), carboxylic acids (RCOOH, where R is anysuitable alkyl group as above), and radical oxygen compounds (eg., O,O₂, O₃, and OH radicals produced by heat, hot-wires, and/or plasma).

In some embodiments, the thickness of the third layer can be controlled,for example, by controlling the number of pulses in the ALD process, orby controlling the sputtered deposited time in a sputter depositionprocess. The third layer thickness can regular the spacing of the metalnanoparticles, which can affect the performance of the memory cellswhich have the nanoparticles embedded in the switching layers.

In operation 740, a fourth layer is deposited over the third layer. Thefourth layer can contain a plurality of metal nanoparticles. The metalnanoparticles can include a metal component, such as gold, copper,silver, tungsten, aluminum, titanium, cobalt, or nickel. The size of themetal nanoparticles can be less than 100 nm, such as less than 50 or 10nm, or can be between 1 and 5 nm. The fourth layer can fromnanoparticles inside the switching layer. The fourth layer depositioncan be omitted, for example, in memory configurations that do notrequire nanoparticles in the switching layer.

The fourth layer can be formed by solvent coating. For example, asolution can be prepared, which contains the nanoparticles. The solutioncan be spread over the first layer, for example, by liquid coating,spray coating, or vapor coating. The solvent can be vaporized, forexample, by substrate heating, leaving the nanoparticles dispersed onthe first layer.

The deposition process of the third and fourth layers can be repeated,for example, to form multiple layers of nanoparticles in a layer ofswitching material. For example, in operation 750, a fifth layer can bedeposited over the fourth layer. In some embodiments, the fourth layercan include only the metal nanoparticles, and thus the fifth layer canbe deposited over the third layer in areas not covered by thenanoparticles. The fifth layer can be operable as a resistive switchinglayer, or a portion of the resistive switching layer, e.g., the fifthlayer can be combined with the third layer to form the resistiveswitching layer.

In operation 760, a sixth layer is deposited over the fifth layer. Thesixth layer can contain a plurality of metal nanoparticles. The metalnanoparticles can include a metal component, such as gold, copper, orsilver. The size of the metal nanoparticles can be less than 100 nm,such as less than 50 or 10 nm, or can be between 1 and 5 nm. The sixthlayer can from nanoparticles at the interface of the switching layerwith the electrode. The sixth layer deposition can be omitted, forexample, in memory configurations that do not require nanoparticles atthe electrode/switching layer interface.

In operation 770, a seventh layer can be deposited over the sixth layer.The seventh layer can be operable as a second or top electrode. The topelectrode can include titanium nitride or platinum. The top electrodemay be formed using ALD, CVD, sputtering, or some other techniques. Thetop electrode may have any thickness, for example between about 5 nm andabout 500 nm thick.

FIG. 8 illustrates a micelle solution according to some embodiments. Asolution can be prepared, including a mixture of two components, such aswater and solvent. The solvent can be an organic solvent, such asmethane, benzene, octane, butanol, and any other types of solvents. Ametal containing chemical can be added to the solution. The metalcontaining chemical can be selected to be soluble in the solution, suchas soluble in water. A surfactant can be added to the solution. Thesurfactant can include molecules with a hydrophobic tail 844 and ahydrophilic head 842. The surfactant molecules can be arranged to formmicelles 800, having the surfactant head 842 arranged in a sphere withthe tail extended outward. A component of the solution, such as water846, can be trapped inside the micelles, with the other component, suchas the solvent 848, staying outside the micelles. Since the metalcontaining chemical 840 is soluble in water, the metal containingchemical can also be trapped inside the micelles. After introducing areduction chemical to the solution, with the reduction chemical alsosoluble in water, the reduction chemical can react with the metalcontaining chemical to form metal nanoparticles 840.

The size 824 of the metal nanoparticles 840 can be controlled by theconcentration of the metal containing chemical in the solution. Forexample, the metal in the metal containing chemical 846 that is trappedinside a micelle can all be reduced to form the metal nanoparticles.Thus the size of the metal nanoparticles is dictated by the amount ofmetal in the micelles.

The spacing 826 between the metal nanoparticles can be dictated by thelength of the tail of the surfactant molecules. Thus a surfactant with along polymer chain can provide a micelle solution with large spacingbetween metal nanoparticles.

FIG. 9 illustrates a schematic representation of atomic layer depositionapparatus for fabricating ReRAM cells according to some embodiments. Forclarity, some components of apparatus 900 are not included in thisfigure, such as a wafer-loading port, wafer lift pins, and electricalfeedthroughs. Apparatus 900 includes deposition chamber 902 connected toprocessing gas delivery lines 904. While FIG. 9 illustrates threedelivery lines 904, any number of delivery lines may be used. Each linemay be equipped with a valve and/or mass flow controller 906 forcontrolling the delivery rates of processing gases into depositionchamber 902. In some embodiments, gases are provided into delivery port908 prior to exposing substrate 910 to processing gases. Deliver port908 may be used for premixing gases (e.g., precursors and diluents) andeven distribution of gases over the surface of substrate 910. Deliveryport 908 is sometimes referred to as a showerhead. Delivery port 908 mayinclude a diffusion plate 909 having with multiple holes for gasdistribution.

Deposition chamber 902 encloses substrate support 912 for holdingsubstrate 910 during its processing. Substrate support 912 may be madefrom a thermally conducting metal (e.g., W, Mo, Al, Ni) or other likematerials (e.g., a conductive ceramic) and may be used to maintain thesubstrate temperature at desired levels. Substrate support 912 may beconnected to drive 914 for moving substrate 910 during loading,unloading, process set up, and sometimes even during processing.Deposition chamber 902 may be connected to vacuum pump 916 forevacuating reaction products and unreacted gases from deposition chamber902 and for maintaining the desirable pressure inside chamber 902.

Apparatus 900 may include system controller 920 for controlling processconditions during electrode and resistive switching layer deposition andother processes. Controller 920 may include one or more memory devicesand one or more processors with a CPU or computer, analog and/or digitalinput/output connections, stepper motor controller boards, etc. In someembodiments, controller 920 executes system control software includingsets of instructions for controlling timing, gas flows, chamberpressure, chamber temperature, substrate temperature, RF power levels(if RF components are used, e.g., for process gas dissociation), andother parameters. Other computer programs and instruction stored onmemory devices associated with controller may be employed in someembodiments.

FIGS. 10A-10B illustrate a schematic representation of resistiveswitching ReRAM cell according to some embodiments. FIG. 10A shows across section view, and FIG. 10B shows a top view of a ReRAM cell.Resistive switching ReRAM cell 1000 includes substrate 1090, which mayinclude a signal line. Alternatively, bottom electrode 1010 may serve asa signal line. Substrate 1090 provides a surface for deposition ofbottom electrode 1010. Bottom electrode 1010 is disposed betweensubstrate 1090 and resistive switching layer 1020. Top electrode 1030 isprovided above resistive switching layer 1020.

Resistive switching layer 1020 can include a metal oxide material, suchas hafnium oxide, aluminum oxide, zirconium oxide, or a combinationthereof. In addition, the switching layer 1020 can include a 3D array ofmetal nanoparticles 1022, which can be distributed in rows and columnswithin the switching layer 1020. For example, the metal nanoparticles1022 can have a lateral spacing 1025, e.g., along the x and y directionsparallel to the surface of the switching layer 1020. The metalnanoparticles 1022 can have a vertical spacing 1027, e.g., along the zdirection perpendicular to the surface of the switching layer 1020. Themetal nanoparticles 1022 can have a size 1024.

The size 1024 of the metal nanoparticles, and the spacing of the metalnanoparticles, e.g., the lateral spacing 1025 and the vertical spacing1027, can be optimized to improve the performance of the memory device.For example, these parameters can be designed to eliminate the formingoperation of the switching layer, and/or reducing the programmingvoltages of the memory cell, thus reducing the power consumption of thememory devices.

The material of resistive switching layer 1020 can be substantiallyamorphous or nanocrystalline after formation of this layer. In someembodiments, resistive switching layer 1020 remains substantiallyamorphous after further processing of the layer, such as annealing,applying a formation voltage, and other operations. Furthermore, in someembodiments, resistive switching layer 1020 remains substantiallyamorphous during operation of ReRAM cell, i.e., applying switchingvoltages and reading voltages that drive corresponding currents.

In some embodiments, the thickness of restive switching layer 1020 isless than about 30 nm, such as between about 2 and 30 nm or, morespecifically, between about 4 and 7 nm, for example, about 5 nm. Thethickness of top and bottom electrodes 1010 and 1030 may be at leastabout 3 and 300 nm or, more specifically, between about 30 and 50 nm. Insome embodiments, the thickness of one or both electrodes is less than 5nm. Such electrodes may be deposited using ALD techniques.

In some embodiments, the size of the metal nanoparticles can be lessthan 50 nm, such as between 1 and 10 nm, or between 1 and 5 nm. In someembodiments, the lateral spacing of the metal nanoparticles can be lessthan 1000 nm, such as less than 100 nm, or can be less than 10 nm. Thevertical spacing of the metal nanoparticles can be less than 100 nm,such as between 1 and 10 nm, such as between 1 and 5 nm, or between 0.2and 3 nm.

In some embodiments, the size of the metal nanoparticles and the lateralspacing of the metal nanoparticles can be controlled in the preparationof a micelle solution. For example, the size of the metal nanoparticlescan be regulated by adjusting the concentration of the metal containingchemical in the micelle solution. The lateral spacing of the metalnanoparticles can be regulated by selecting surfactant components havingappropriate block copolymer chain. The vertical spacing of the metalnanoparticles can be regulated by controlling the deposition thicknessof the portion of the switching layer 1020 between rows of metalnanoparticles. In some embodiments, the deposition thickness is lessthan 10 nm, such as less than 5 nm, or between 0.2 and 3 nm,

Electrodes 1010 and 1030 provide electronic communication to resistiveswitching layer 1020 of ReRAM cell 1000. One or both electrodes maydirectly interface resistive switching layer 1020 or be spaced apart byother layers, such as barrier layers, current limiting layer, and thelike. Depending on the materials used for electrode construction, theelectrode (e.g., an electrode formed from titanium nitride) itself mayalso serve as an adhesion layer and/or barrier layer. In someembodiments, one or both electrodes are also function as signal lines(i.e., bit and/or word lines) and are shared by other ReRAM cells.

Some examples of electrode materials include titanium nitride (TiN), andplatinum. In some embodiments, barrier layers, adhesion layers,antireflection coatings and/or other layers may be used with theelectrodes and to improve device performance and/or aid in devicefabrication.

In some embodiments, one electrode may be a higher work functionmaterial, and the other electrode may be a lower work function materialthan the resistive switching layer. For example, an electrode caninclude titanium nitride and the other electrode can include platinum.Platinum is a noble metal (i.e., a metal with a low absolute value freeenergy change (|ΔG|) of oxide formation), which may be used for oneelectrode. The other electrode may be a lower work function material,such as titanium nitride. In some embodiments, the reset pulse at theelectrode having the higher work function may be a positive pulse.

In some embodiments, one or both electrodes may be multi-layerelectrodes formed by one or more different materials. For example, anelectrode can include a base layer and capping layer. The base layer mayinclude platinum, or titanium nitride. The capping layer may includetungsten, tungsten carbon nitride, and/or tungsten carbon. Themulti-layer electrodes can be used to improve adhesion properties andperformance of memory elements in some configurations and embodiments.

ReRAM cell 1000 may include another layer (not shown) that is operableas a current limiting layer. A material for this layer may have asuitable work function for controlling the electron flow through ReRAMcell. This specific selection may alter the magnitude of the generatedswitching currents. In some embodiments, the current limiting layer isused to increase or decrease the formed barrier height at the interfacewith resistive switching layer 1020. This feature is used to improvecurrent flowing characteristics and reduce the magnitude of theswitching currents. It should be noted that these changes in the barrierheight will generally not affect the current ratio (I_(ON)/I_(OFF)), andthus not impacts detectability of different resistive states.

In some embodiments, the current limiting layer is between about 5 and300 nm thick, such as between about 5 and 20 nm. This layer may beformed from a material that has a resistivity of between about 5 Ω-cmand 500 Ω-cm, such as between about 50 Ω-cm and 350 Ω-cm. In someembodiments, the current limiting layer is formed such that itsresistance (R_(RL)) is between about 30 kΩ and about 30 MΩ, such asbetween about 300 kΩ and about 3 MΩ.

Resistivity is an intrinsic property of the material and can becontrolled by adjusting the composition of the material. Some specificexamples include adding alloying elements or doping atoms and/oradjusting the morphological structure of the materials, (e.g., shiftingfrom amorphous to crystal structure). In some embodiments, a currentlimiting layer may include titanium oxide doped with niobium, tin oxidedoped with antimony, or zinc oxide doped with aluminum.

Other examples of materials suitable for the current limiting layerinclude titanium nitride (Ti_(x)N_(y)), tantalum nitride (Ta_(x)N_(y)),silicon nitride (Si_(x)N_(y)), hafnium nitride (Hf_(x)N_(y)) or titaniumaluminum nitride (Ti_(x)Al_(y)N_(z)) layer. Such layers may be formedusing an ALD, CVD or PVD process as further described below.

FIGS. 11A-11B illustrate flowcharts for fabricating a resistiveswitching layer of a memory device according to some embodiments. InFIG. 11A, an array of metal nanoparticles can be formed on a layer usinga micelle solution (operation 1110). The array of nanoparticles can be a2D array along the exposed surface of the layer. The layer can includean electrode layer, and the array of metal nanoparticles can form at thesurface of the electrode layer. Thus after a subsequent switching layeris deposited on the electrode, the array of metal nanoparticles can bedisposed at the interface of the electrode and the switching layer. Thelayer can include a switching layer, and the array of metalnanoparticles can form at the surface of the switching layer. Thus aftera second electrode layer is deposited on the switching layer, the arrayof metal nanoparticles can be disposed at the interface of the secondelectrode and the switching layer. The layer can include a first portionof a switching layer. Thus after a second portion of the switching layeris deposited on the first portion, the array of metal nanoparticles canbe disposed inside the switching layer.

The micelle solution can be prepared to have metal nanoparticlesembedded within the micelles. For example, a micelle solution havinggold nanoparticles in the micelles can be prepared using gold chloride,soap surfactant, solution mixture of water, octane and butanol, andsodium borohydride as described above. The spacing between the micellescan be controlled by using polymer having different chain length. Forexample, different surfactant can create micelles with different tail'slengths, which can determine the spacing between the micelles.

The spacing between the micelles can be configured to improve aperformance characteristic of a memory cell using the metalnanoparticles, such as a power consumption characteristic or arepeatability or reliability characteristic. For example, densermicelles, e.g., micelles with shorter spacing between them, can formdenser array of metal nanoparticles, which can provide more seedlocations for conductive filaments. The high density of conductivefilaments can lower a programming voltage for the memory cell, sincedefects in the switching layer can have a shorter time to travel to theseed locations. The lower programming voltage can improve a powerrequirement characteristic of the memory cell, thus can improve theperformance of the memory cell. Denser array of metal nanoparticles canalso improve the repeatability or the reliability of the memory cell,for example, due to the simpler or easier to form filaments.

In FIG. 11B, 3D control of the metal nanoparticles can be achieved. Thecontrol of the lateral spacing can be achieved by the block copolymerchain length of the micelles in the micelle solution, as describedabove. In addition, the control of the vertical spacing can be achievedby the deposition process of the portions of the switching layer. Themultiple dimension control of the metal nanoparticles can lead to themultiple controls of the filament formation, which can provideoptimization of the memory cells having the embedded nanoparticles.

In operation 1120, a first layer is deposited. The first layer can bedeposited on a substrate, on an electrode, on an electrode having anarray of metal nanoparticles, on a portion of a switching layer, or on aportion of a switching layer having an array of metal nanoparticles. Thefirst layer can be a portion of a switching layer. The first layer canbe deposited by ALD. The thickness of the first layer can be configuredto improve a performance characteristic of a memory device such as apower consumption characteristic or a repeatability or reliabilitycharacteristic. For example, the thickness of the first layer candetermine the vertical spacing of metal nanoparticles, such as theseparation between a bottom array and a top array of nanoparticles.Controlling the vertical spacing of the nanoparticles can provide animprovement or an optimization of a power consumption or a reliabilityof the memory cells.

In operation 1130, an array of metal nanoparticles can be formed on thefirst layer by a micelle solution. The lateral spacing of thenanoparticles can be controlled by the preparation of the micellesolution, as described above. The spacing between the micelles can alsobe configured to improve a performance characteristic of a memorydevice.

In operation 1140, the process can be repeated. For example, anotherfirst layer can be deposited, with the thickness configured to improve aperformance characteristic of a memory device. Alternatively, anotherfirst layer and another array of nanoparticles can be formed on theexisting first layer and first array of nanoparticles.

FIG. 12 illustrates a flowchart for forming a memory device according tosome embodiments. In operation 1210, a substrate is provided wherein thesubstrate comprises a first layer, wherein the first layer is operableas a first electrode. In operation 1220, a second layer is deposited onthe first layer, wherein the second is operable as a resistive switchinglayer. In operation 1230, a third layer is deposited on the secondlayer, wherein the third layer comprises metal nanoparticles disposed inmicelles. The third layer can include an array of nanoparticles. Inoperation 1240, the process is repeated, e.g., another first layer andanother second layer are formed on the existing first and second layers.In operation 1250, a fourth layer is deposited on the third layer,wherein the fourth layer is operable as a resistive switching layer. Inoperation 1260, a fifth layer is deposited on the fourth layer, whereinthe fifth layer is operable as a second electrode.

In some embodiments, the embedded nanoparticles memory structures can beused in memory arrays, such as cross point memory arrays. FIG. 13A-13Billustrates memory arrays according to some embodiments. A briefdescription of memory arrays will now be described with reference toFIGS. 13A and 13B to provide better understanding to various aspects ofthermally isolating structures provided adjacent to ReRAM cells and, insome examples, surrounding the ReRAM cells. ReRAM cells described abovemay be used in memory devices or larger integrated circuits (IC) thatmay take a form of arrays. FIG. 13A illustrates a memory array includingnine ReRAM cells according to some embodiments. In general, any numberof ReRAM cells may be arranged into one array. Connections to each ReRAMcell 1302 are provided by signal lines 1304 and 1306, which may bearranged orthogonally to each other. ReRAM cells 1302 are positioned atcrossings of signal lines 1304 and 1306 that typically define boundariesof each ReRAM cell in array 1300.

Signal lines 1304 and 1306 are sometimes referred to as word lines andbit lines. These lines are used to read and write data into each ReRAMcell 1302 of array 1300 by individually connecting ReRAM cells to readand write controllers. Individual ReRAM cells 1302 or groups of ReRAMcells 1302 can be addressed by using appropriate sets of signal lines1304 and 1306. Each ReRAM cell 1302 typically includes multiple layers,such as top and bottom electrodes, resistive switching layer, embeddedresistors, embedded current steering elements, and the like, some ofwhich are further described elsewhere in this document. In someembodiments, a ReRAM cell includes multiple resistive switching layersprovided in between a crossing pair of signal lines 1304 and 1306.

As stated above, various read and write controllers may be used tocontrol operations of ReRAM cells 1302. A suitable controller isconnected to ReRAM cells 1302 by signal lines 1304 and 1306 and may be apart of the same memory device and circuitry. In some embodiments, aread and write controller is a separate memory device capable ofcontrolling multiple memory devices each one containing an array ofReRAM cells. Any suitable read and write controller and array layoutscheme may be used to construct a memory device from multiple ReRAMcells. In some embodiments, other electrical components may beassociated with the overall array 1300 or each ReRAM cell 1302. Forexample, to avoid the parasitic-path-problem, i.e., signal bypasses byReRAM cells in their low resistance state (LRS), serial elements with aparticular non-linearity must be added at each node or, morespecifically, into each element. Depending on the switching scheme ofthe ReRAM cell, these elements can be diodes or varistor-type elementswith a specific degree of non-linearity. In the same other embodiments,an array is organized as an active matrix, in which a transistor ispositioned at each node or, more specifically, embedded into each cellto decouple the cell if it is not addressed. This approach significantlyreduces crosstalk in the matrix of the memory device.

In some embodiments, a memory device may include multiple array layersas, for example, illustrated in FIG. 13B. In this example, five sets ofsignal lines 1314 a-b and 1316 a-c are shared by four ReRAM arrays 1312a-c. As with the previous example, each ReRAM array is supported by twosets of signal lines, e.g., array 1312 a is supported by 1314 a and 1316a. However, middle signal lines 1314 a-b and 1316 b, each is shared bytwo sets ReRAM arrays. For example, signal line set 1314 a providesconnections to arrays 1312 a and 1312 b. Top and bottom sets of signallines 1316 a and 1316 c are only used for making electrical connectionsto one array. This 3-D arrangement of the memory device should bedistinguished from various 3-D arrangements in each individual ReRAMcell.

Although the foregoing examples have been described in some detail forpurposes of clarity of understanding, the invention is not limited tothe details provided. There are many alternative ways of implementingthe invention. The disclosed examples are illustrative and notrestrictive.

What is claimed is:
 1. A resistive random access memory cell comprising:a first layer operable as a first electrode; a second layer operable asa resistive switching layer, wherein the second layer is disposed abovethe first layer, wherein the second layer comprises one or more arraysof metal nanoparticles, wherein the arrays of metal nanoparticles aredisposed inside the second layer; a third layer operable as a secondelectrode, wherein the third layer is disposed above the second layer.2. A memory cell as in claim 1, wherein the array of metal nanoparticlesis disposed at an interface of the switching layer and an electrode. 3.A memory cell as in claim 1, wherein a spacing between the array ofmetal nanoparticles and an electrode is between 1 and 10 nm.
 4. A memorycell as in claim 1, wherein the second layer comprises two or morearrays of metal nanoparticles, wherein a spacing between the two arraysof metal nanoparticles is between 1 and 10 nm.
 5. A memory cell as inclaim 1, wherein a spacing between metal particles in the array of metalnanoparticles is between 1 and 10 nm.
 6. A memory cell as in claim 1,wherein a size of the metal particles is between 1 and 5 nm.
 7. A memorycell as in claim 1, wherein the second layer comprises two or morearrays of metal nanoparticles, wherein the two or more arrays of metalnanoparticles are aligned between the two electrodes.
 8. A memory cellas in claim 1, wherein the second layer comprises two or more arrays ofmetal nanoparticles, wherein the two or more arrays of metalnanoparticles are staggered between the two electrodes.
 9. A method offorming a resistive random access memory cell, the method comprising:providing a substrate comprising a first layer, wherein the first layeris operable as a first electrode; depositing a second layer over thefirst layer, wherein the second layer comprises a first material whichis operable as a resistive switching layer; depositing an array of metalnanoparticles on the second layer; depositing a third layer on the arrayof metal nanoparticles, wherein the third layer comprises the firstmaterial; depositing a fourth layer over the third layer, wherein thefourth layer is operable as a second electrode.
 10. A method as in claim9, further comprising depositing a second array of metal nanoparticleson the first layer before forming the second layer.
 11. A method as inclaim 9, further comprising repeating the steps of depositing an arrayof metal nanoparticles and depositing the third layer.
 12. A method asin claim 9, further comprising depositing a third array of metalnanoparticles before forming the fourth layer.
 13. A method as in claim9, further comprising annealing the first, second, and third layers at atemperature between 400 and 750 C.
 14. A method as in claim 9, whereindepositing the second layer comprises using atomic layer deposition(ALD).
 15. A method as in claim 9, wherein depositing the array of metalnanoparticles comprises coating with a micelle solution, wherein themicelle solution comprises micelles, wherein micelles comprises metalnanoparticles.
 16. A method of improving a performance of a resistiverandom access memory cell, wherein the resistive memory cell comprises aswitching layer disposed between two electrodes, the method comprising:forming an array of metal nanoparticles in the switching layer;controlling a vertical spacing of the metal nanoparticles, wherein thevertical spacing comprises a distance along a direction perpendicular toa surface of the electrodes; controlling a lateral spacing of the metalnanoparticles, wherein the lateral spacing comprises a distance along adirection parallel to a surface of the electrodes.
 17. A method as inclaim 18, wherein controlling a vertical spacing of the metalnanoparticles comprises controlling a deposition thickness of theswitching layer.
 18. A method as in claim 18, wherein controlling alateral spacing of the metal nanoparticles comprises controlling aseparation of the metal nanoparticles in a micelle solution, wherein themicelle solution is used to form the array of metal nanoparticles in theswitching layer.
 19. A memory cell as in claim 18, wherein thedeposition thickness of the switching layer is less than 10 nm.
 20. Amemory cell as in claim 18, wherein the separation of the metalnanoparticles in a micelle solution is less than 10 nm.